(1) Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a programmable read only memory (PROM) of, for example, a fuse type or a PN junction shortcircuiting type.
(2) Description of the Related Art
A fuse type PROM has a fuse which is melted by allowing a large current to pass through the fuse in order to write data into a selected memory cell. A PN junction shortcircuiting type of PROM has a PN junction which is broken by allowing a large current to pass through the PN junction, so that data is written into a selected memory cell. In either type of PROM, it is possible to write data once in the memory cell.
FIG. 1A is a block diagram of a such conventional PROM. The PROM in FIG. 1A is made up of a memory cell array 11, an address buffer 12, an address buffer 13, a chip enable circuit 14, a word driver/programming current absorbing circuit 15, a programming current applying circuit 16, a sense amplifier 17 and an output buffer 18. A row address signal comprising of address bits X0-Xn is buffered in the address buffer 12 and then applied to the word driver/programming current absorbing circuit 15. A column address composed of address bits Y0-Yn is buffered in the address buffer 13, and applied to the programming current applying circuit 16 and the sense amplifier 17. A chip enable signal CE is input to the chip enable circuit 14 and the programming current applying circuit 16. The chip enable circuit 14 activates the output buffer circuit 18 in response to the chip enable signal CE. The programming current applying circuit 16 applies a programming current to at least one bit line 21 on the basis of the column address read out from the address buffer 13 as well as readout data D.sub.0 -D.sub.1 obtained on the output side of the output buffer 18. The word driver/programming current absorbing circuit 15 selects at least one word line 22. When data is written into a memory cell 23, a programming current I.sub.PRG is allowed to pass through the memory cell 23, as shown by the solid line shown in FIG. 1A. Meanwhile, when data is read out from the memory cell 23, a read current I.sub.READ passes through the memory cell 23, as shown by the broken line shown in FIG. 1A.
FIG. 1B is a circuit diagram of the word driver/programming current absorbing circuit 15. The circuit configuration shown in FIG. 1B is provided for each of the word lines 22. The circuit in FIG. 1B comprises two Schottky transistors Q1 and Q2 and four resistors R1-R4. The resistors R1-R3 are connected to a power supply line maintained at a power supply voltage Vcc. When data is written into the memory cell 23, the transistors Q1 and Q2 are turned ON, and the programming current I.sub.PRG passes through the bit line 21, the memory cell 23, the word line 22 and the transistor Q2. In order to write data into the memory cell 23 at a high speed, the transistors Q1 and Q2, particularly transistor Q2, must have a large area (a large mutual conductance).
In order to reduce the sizes of the transistors Q1 and Q2, as shown in FIG. 2A, it is possible to provide each word line 22 with a programming current absorbing circuit (PCAC) 24 separately from a word driver 15A having the same configuration as that of the circuit 15 except for the transistor size. Each programming current absorbing circuit 24 as shown in FIG. 2B, comprises a transistor Q3, a base current supply circuit BCSC 25, and a load resistor R7. The collector of the transistor Q3 is connected to the corresponding word line 22, and the base thereof is supplied with a base current generated by the base current supply circuit 25, which is connected to a power source line which is maintained at a programming voltage PV.sub.CE for use in data writing. The emitters of the transistors Q3 are maintained at a predetermined potential V.sub.A equal to, for example, ground potential GND. The collector of the transistors Q3 are coupled to the resistors R7 via the base current supply circuits 25. The transistors Q3 are of a size larger than that of the transistors Q2. When the memory cell 23 is programmed, most of the programming current I.sub.PRG passes through the bit line 21, the memory cell 23, the word line 22 and the transistor Q3. Thus, it is possible to prevent a large current from passing through the transistor Q2.
As shown in FIG. 2C, the base current supply circuit 25 comprises of transistors Q4 and Q5, and resistors R5-R8. The sizes of the transistors Q4 and Q5 are smaller than the size of the transistor Q3. The NPN type transistor Q4 and the PNP type transistor Q5 form an SCR (Silicon Controlled Rectifier).
However, the circuit configuration shown in FIGS. 2A through 2C has the following disadvantage. Each word line 22 which is not selected, is maintained at a high potential approximately equal to Vcc, so that the transistor Q4 is OFF and thus the transistors Q3 and Q5 are also OFF. However, if an instantaneous noise signal occurs in one or a plurality of the word lines 21 which are not being selected while one of the word lines 21 is being selected, and the potential(s) of the word line(s) 21 slightly decreases temporarily, the transistor Q4 may be turned ON, and thus the transistors Q5 and Q3 are turned ON. As a result, the corresponding word line(s) is (are) turned ON, and data is erroneously written into the corresponding memory cell(s) 23. Thus, the word lines 21 do not have sufficient potential margins.